There are currently a limited number of ways for producing through-encapsulant vias (TEVs).
In some cases, pre-produced via bars 102 may be embedded in encapsulant 104 using a simple process sequence at an embedding level, like dice as shown in FIG. 1. As shown in FIG. 1, the woven glass fiber of the embedded via bar 102 is visible. These via bars 102 may be costly, and moreover, have very limited via density as they may be manufactured using printed circuit board (PCB) technology. The via bars 102 may be simply plugged in the offline PCB production line. Therefore, typical via pitches may be in the range of several hundred micrometers, e.g. about 300 μm. Furthermore, there may be a limited degree of design freedom because the vias may not be located everywhere. Furthermore, usually only a very limited number of via bars may be arranged, for example only one via bar per side.
TEVs may also be formed by forming a hole, i.e. via drilling by a laser. This may be followed by seed layer deposition, and plating in the holes. Wafers having a thickness of about 250 μm may be difficult to handle. While vias may be located everywhere beside the die(s) (not shown), laser drilling through encapsulant material may be challenging, due to the presence of inorganic filler particles in the encapsulant material. Typically achievable via diameters, may generally be larger than about 100 μm, and therefore, via density may also be rather limited. Further, via pitch may be in the range of about 300 μm. The filler particles tend to cause undercuts, thereby making deposition of the seed layer very difficult. Particular with thicker wafers, e.g. 450 μm thick, the aspect ratio of the vias and the undercuts tend to cause interrupted connections in the seed layer. This may lead subsequently to problems will via filling by electroplating, e.g. by electroplating cooper. The discontinuity in the seed layer, may mean that the vias cannot or may not be totally or substantially filled with metal. Plugging may also be difficult, and buried vias may generally not be acceptable.
In other cases, elastic contact elements may be positioned between interposer substrates which surround a semiconductor chip.